1. Field of the Invention
The present invention relates to a semiconductor memory device and, more specifically, to a semiconductor memory device in which state of storage is determined based on capacitance stored in a capacitor element forming a memory cell.
2. Description of the Background Art
A DRAM (Dynamic Random Access Memory) as a representative example of a semiconductor memory device has been used in various electronic equipment as most suitable for attaining higher degree of integration and larger capacity of semiconductor devices, as the structure of the memory cell itself is simple, that is, the memory cell has one-element type structure (one transistor and one capacitor).
FIG. 30 is a schematic diagram representing a configuration of memory cells arranged in a matrix of rows and columns in a memory cell array of a DRAM.
Referring to FIG. 30, a memory cell 1000 includes an n-channel MOS (Metal Oxide Semiconductor) transistor 1002, and a capacitor 1004. One of source/drain of n-channel MOS transistor 1002 is electrically connected to a bit line 1008, while the other of the source/drain is electrically connected to one electrode of capacitor 1004. The gate of n-channel MOS transistor 1002 is electrically connected to a word line 1006. The other electrode of capacitor 1004 is electrically connected to a cell plate potential 1010.
The n-channel MOS transistor 1002 is driven by word line 1006 that is activated only at the time of data writing and at the time of data reading, and the transistor is turned ON at the time of data writing and data reading only and otherwise kept OFF.
Capacitor 1004 stores binary information xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d dependent on whether charges are stored or not. A voltage corresponding to the binary information xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d is applied from bit line 1008 through n-channel MOS transistor 1002 to capacitor 1004, whereby capacitor 1004 is charged/discharged, attaining data writing.
Specifically, when data xe2x80x9c1xe2x80x9d is to be written, bit line 1008 is precharged to a power supply voltage Vcc, word line 1006 is activated so that n-channel MOS transistor 1002 is turned ON, the power supply voltage Vcc is applied from bit line 1008 through n-channel MOS transistor 1002 to capacitor 1004, and charges are stored in capacitor 1004. The state in which the charges are stored in capacitor 1004 corresponds to the data xe2x80x9c1xe2x80x9d.
When data xe2x80x9c0xe2x80x9d is to be written, bit line 1008 is precharged to the ground voltage GND, word line 1006 is activated so that n-channel MOS transistor 1002 is turned ON, and charges are discharged from capacitor 1004 through n-channel MOS transistor 1002 to bit line 1008. The state in which charges are not stored in capacitor 1004 corresponds to the stored data xe2x80x9c0xe2x80x9d.
When data is to be read, bit line 1008 is precharged to a voltage Vcc/2 in advance, word line 1006 is activated so that n-channel MOS transistor 1002 is turned ON, and bit line 1008 and capacitor 1004 are conducted. Thus, a slight change in voltage in accordance with the state of storage of capacitor 1004 appears on bit line 1008, and a sense amplifier, not shown, amplifies the slight change in voltage to the voltage Vcc or to the ground voltage GND. The voltage level of bit line 1008 corresponds to the state of the read data.
The data reading operation described above is a destructive reading. Therefore, word line 1006 is again activated while the bit line 1008 is amplified to the voltage Vcc or the ground voltage GND in accordance with the read data, and the capacitor 1004 is re-charged through the similar operation as the data writing operation described above. Thus, the data once destroyed for data reading is recovered to the original state.
In a memory cell of the DRAM, however, charges of the capacitor 1004 that correspond to the stored data leak by some cause or other, and gradually lost. In other words, the stored data is lost with time. Therefore, in the DRAM, before it becomes impossible to detect the change in voltage of bit line 1008 corresponding to the stored data in data reading, a refresh operation is performed, in which the data is once read and written again.
In the DRAM, it is necessary to perform the refresh operation constantly and periodically on every memory cell. Therefore, the DRAM is in this point disadvantageous in view of higher speed of operation and lower power consumption. In order to attain higher speed of operation and lower power consumption, the DRAM is inferior to an SRAM (Static Random Access Memory) that does not require any refresh operation.
An object of the present invention is to provide a semiconductor memory device that does not require the refresh operation.
According to the present invention, the semiconductor memory device includes a plurality of memory cells arranged in a matrix of rows and columns, and each of the plurality of memory cells has its state of storage determined based on the capacitance stored in a capacitor element. Each of the plurality of memory cells includes a transfer gate transistor, a capacitor element, a first inverter and a second inverter. The transfer gate transistor has a pair of source/drain. The capacitor element has first and second electrodes opposed to each other to allow storage of capacitance, and the first electrode is electrically connected to one of the pair of source/drain. The first inverter has an input node electrically connected to one of the pair of source/drain. The second inverter has an input node electrically connected to an output node of the first inverter, and an output node electrically connected to an input node of the first inverter. The capacitor element has the first electrode electrically connected to the output node of the second inverter, and the second electrode electrically connected to the output node of the first inverter. The state of storage is determined based on the capacitance stored in the capacitor element.
According to the semiconductor memory device of the present invention, in each of the plurality of memory cells arranged in a matrix of rows and columns, the first and second inverters are cross coupled. Further, the first electrode of the capacitor element storing capacitance is electrically connected to the output node of the second inverter, and the second electrode is electrically connected to the output node of the first inverter. Thus, leakage of charges from the capacitor element is compensated for by the cross coupled circuit. As a result, it becomes possible to prevent the state of storage from being lost because of leakage of charges, without necessitating any refresh operation.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.